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(parent: 6613476) | patch
clk: rockchip: rk3568: Add PLL rate for 128MHz
authorChris Morgan <macromorgan@hotmail.com>
Tue, 23 Jan 2024 21:21:10 +0000 (15:21 -0600)
committerHeiko Stuebner <heiko@sntech.de>
Thu, 25 Jan 2024 19:59:43 +0000 (20:59 +0100)
commitb3244351e2b39bd49aba780ea204f0f2a45a4725
treeedaa2cf442de9fcc70d2291e93ed8c592e5ec8d9tree | snapshot
parent6613476e225e090cc9aad49be7fa504e290dd33dcommit | diff
clk: rockchip: rk3568: Add PLL rate for 128MHz

Add PLL rate for 128MHz to allow the panel for the Anbernic RG-ARC
series to run at 60hz.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Link: https://lore.kernel.org/r/20240123212111.202146-4-macroalpha82@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/clk-rk3568.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git