target/riscv: support for 128-bit M extension
authorFrédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Thu, 6 Jan 2022 21:01:04 +0000 (22:01 +0100)
committerAlistair Francis <alistair.francis@wdc.com>
Sat, 8 Jan 2022 05:46:10 +0000 (15:46 +1000)
commitb3a5d1fbebab2098d0c3cdd3732c25f5cfbe5cbc
treede45abe8d17924f957c7f02a41f724bfbfc7724d
parent7fd40f8679ceed388d82902e9be05ae136cf09cd
target/riscv: support for 128-bit M extension

Mult are generated inline (using a cool trick pointed out by Richard), but
for div and rem, given the complexity of the implementation of these
instructions, we call helpers to produce their behavior. From an
implementation standpoint, the helpers return the low part of the results,
while the high part is temporarily stored in a dedicated field of cpu_env
that is used to update the architectural register in the generation wrapper.

Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-15-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.h
target/riscv/helper.h
target/riscv/insn32.decode
target/riscv/insn_trans/trans_rvm.c.inc
target/riscv/m128_helper.c [new file with mode: 0644]
target/riscv/meson.build