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(parent: 74523a5) | patch
dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PM
authorSowjanya Komatineni <skomatineni@nvidia.com>
Mon, 21 Dec 2020 21:17:31 +0000 (13:17 -0800)
committerMark Brown <broonie@kernel.org>
Wed, 6 Jan 2021 13:09:27 +0000 (13:09 +0000)
commitb499779761278d6f5339daa230938211d98861ef
treece8680a9c047ba4c5c2a89f7bb61dcf14eaba9d4tree | snapshot
parent74523a5dae0c96d6503fe72da66ee37fd23eb8f5commit | diff
dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PM

Tegra210 QSPI clock output has divider DIV2_SEL which will be enabled
when using DDR interface mode.

This patch adds clock ID for this to dt-binding.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Link: https://lore.kernel.org/r/1608585459-17250-2-git-send-email-skomatineni@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>
include/dt-bindings/clock/tegra210-car.h diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git