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target-xtensa: implement MISC SR
authorMax Filippov <jcmvbkbc@gmail.com>
Wed, 5 Dec 2012 03:15:24 +0000 (07:15 +0400)
committerBlue Swirl <blauwirbel@gmail.com>
Sat, 8 Dec 2012 18:48:26 +0000 (18:48 +0000)
commitb7909d81f7658f64bba0faed83e7c2fd6a52fcba
tree532268ec2f2f26c3321770fe23a4f7fab68cd6f5tree | snapshot
parent53593e90d13264dc88b3281ddf75ceaa641df05acommit | diff
target-xtensa: implement MISC SR

The Miscellaneous Special Registers Option provides zero to four scratch
registers within the processor readable and writable by RSR, WSR, and
XSR. These registers are privileged. They may be useful for some
application-specific exception and interrupt processing tasks in the
kernel. The MISC registers are undefined after reset.
See ISA, 4.7.3 for details.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-xtensa/cpu.h diff | blob | history
target-xtensa/overlay_tool.h diff | blob | history
target-xtensa/translate.c diff | blob | history
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