mtd: spi-nor: otp: fix access to security registers in 4 byte mode
authorMichael Walle <michael@walle.cc>
Mon, 7 Jun 2021 11:27:41 +0000 (13:27 +0200)
committerVignesh Raghavendra <vigneshr@ti.com>
Wed, 9 Jun 2021 18:04:15 +0000 (23:34 +0530)
commitb97b1a769849beb6b40b740817b06f1a50e1c589
tree81560aafefde0530471951d6a3c8e488cb24944b
parent7ea40b54e83baed17d85567cfae56175def39a55
mtd: spi-nor: otp: fix access to security registers in 4 byte mode

The security registers either take a 3 byte or a 4 byte address offset,
depending on the address mode of the flash. Thus just leave the
nor->addr_width as is.

Fixes: cad3193fe9d1 ("mtd: spi-nor: implement OTP support for Winbond and similar flashes")
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Acked-by: Pratyush Yadav <p.yadav@ti.com>
drivers/mtd/spi-nor/otp.c