target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
authorClément Léger <cleger@rivosinc.com>
Mon, 22 Apr 2024 13:58:36 +0000 (15:58 +0200)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 3 Jun 2024 01:12:11 +0000 (11:12 +1000)
commitba7a1c52975a4068573deea4471535567393c366
treeb7aeeff13cafd40881f78f4d6769414e7de62212
parent039003995047b2f7911142c7c5cfb845fda044fd
target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63

The current semihost exception number (16) is a reserved number (range
[16-17]). The upcoming double trap specification uses that number for
the double trap exception. Since the privileged spec (Table 22) defines
ranges for custom uses change the semihosting exception number to 63
which belongs to the range [48-63] in order to avoid any future
collisions with reserved exception.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu_bits.h