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target/riscv: Move/refactor ISA extension checks
authorTsukasa OI <research_trasio@irq.a4lg.com>
Sun, 15 May 2022 02:56:11 +0000 (11:56 +0900)
committerAlistair Francis <alistair.francis@wdc.com>
Tue, 24 May 2022 00:38:50 +0000 (10:38 +1000)
commitbc573816692357e4c824d5c1df73987d3f0ea0c4
treea1b952cb4057866a81fa8a048389394870d72788tree | snapshot
parent1086504c6f46a2b3be90e887dddb4741bf8c500dcommit | diff
target/riscv: Move/refactor ISA extension checks

We should separate "check" and "configure" steps as possible.
This commit separates both steps except vector/Zfinx-related checks.

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <c3145fa37a529484cf3047c8cb9841e9effad4b0.1652583332.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c diff | blob | history
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