dt-bindings: clock: Add StarFive JH7110 PLL clock generator
authorXingyu Wu <xingyu.wu@starfivetech.com>
Mon, 17 Jul 2023 02:30:34 +0000 (10:30 +0800)
committerConor Dooley <conor.dooley@microchip.com>
Wed, 19 Jul 2023 17:07:48 +0000 (18:07 +0100)
commitbd348ca24d81cca2a27f8ffa12adc8f30f184275
treec70d6233857bc91f11f4b3ef10cabb76bcea8e28
parent06c2afb862f9da8dc5efa4b6076a0e48c3fbaaa5
dt-bindings: clock: Add StarFive JH7110 PLL clock generator

Add bindings for the PLL clock generator on the JH7110 RISC-V SoC.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml [new file with mode: 0644]
include/dt-bindings/clock/starfive,jh7110-crg.h