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(parent: 9e69e76) | patch
target/riscv: machine: Add Control Transfer Record state description
authorRajnesh Kanwal <rkanwal@rivosinc.com>
Wed, 5 Feb 2025 11:18:50 +0000 (11:18 +0000)
committerAlistair Francis <alistair.francis@wdc.com>
Tue, 4 Mar 2025 05:42:54 +0000 (15:42 +1000)
commitbda6522e3f9002040fc223c12457b849328a1d39
tree09a697fc4997e87fa976efa4825b4dd5f0a1849ctree | snapshot
parent9e69e760fdc34a9d13a8c434d6a9fada835a05adcommit | diff
target/riscv: machine: Add Control Transfer Record state description

Add a subsection to machine.c to migrate CTR CSR state

Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250205-b4-ctr_upstream_v6-v6-6-439d8e06c8ef@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/machine.c diff | blob | history
Unnamed repository; edit this file 'description' to name the repository.