hw/char/riscv_htif: Explicit little-endian implementation
authorPhilippe Mathieu-Daudé <philmd@linaro.org>
Fri, 29 Nov 2024 15:43:03 +0000 (16:43 +0100)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 20 Dec 2024 01:22:47 +0000 (11:22 +1000)
commitbe0a70b93f4ff3dda77b9db50ec452f03170ff9a
treecb12fb86e217fcaa22bb1226306017292482b3e1
parenta2ce7f806d894f04cbb541d619cead44cd588725
hw/char/riscv_htif: Explicit little-endian implementation

Since our RISC-V system emulation is only built for little
endian, the HTIF device aims to interface with little endian
memory accesses, thus we can explicit htif_mm_ops:endianness
being DEVICE_LITTLE_ENDIAN.

In that case tswap64() is equivalent to le64_to_cpu(), as in
"convert this 64-bit little-endian value into host cpu order".
Replace to simplify.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241129154304.34946-3-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
hw/char/riscv_htif.c