drm/i915: Use the correct mdclk/cdclk ratio in MBUS updates
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Tue, 2 Apr 2024 15:50:13 +0000 (18:50 +0300)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 4 Apr 2024 13:29:10 +0000 (16:29 +0300)
commitbea9898561f1d38915128c57fd280a91e5048579
tree88f166aacb841dabe1824e7b65c807c1bb2b4a28
parent48b85304c00c3b523a44d4cd96a8160becf3e3a4
drm/i915: Use the correct mdclk/cdclk ratio in MBUS updates

The current cdclk/mbus programming sequence is as follows:
1. intel_set_cdclk_pre_plane_update()
2. update_mbus_pre_enable()
3. intel_set_cdclk_post_plane_update()

when the actual mdclk/cdclk programming is postponed to
intel_set_cdclk_post_plane_update() we must keep using
the old mdclk/cdclk ratio during update_mbus_pre_enable().
This guarantees the programmed ratio matches the rest of
the hardware state (mdlk/cdclk/mbus joining).

v2: Extracted from the vblank synchronized mbus programming patch

Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com> #v1
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240402155016.13733-12-ville.syrjala@linux.intel.com
drivers/gpu/drm/i915/display/intel_cdclk.c
drivers/gpu/drm/i915/display/intel_cdclk.h
drivers/gpu/drm/i915/display/skl_watermark.c