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clk: renesas: rzg2l: Simplify the logic in rzg2l_mod_clock_endisable()
authorClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Tue, 12 Sep 2023 04:51:31 +0000 (07:51 +0300)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 18 Sep 2023 08:05:02 +0000 (10:05 +0200)
commitbecf4a771a12b52dc5b3d2b089598d5603f3bbec
tree234e1042505825a5cdc0a9fb58cc582add0916e4tree | snapshot
parent17939df3c9acd26e4dac1c5943dd8e58e1bcb4e7commit | diff
clk: renesas: rzg2l: Simplify the logic in rzg2l_mod_clock_endisable()

The bitmask << 16 is anyway set on both branches of if thus move it
before the if and set the lower bits of registers only in case clock is
enabled.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230912045157.177966-12-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/rzg2l-cpg.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git