drm/xe: fix pat[2] programming with 2M/1G pages
authorMatthew Auld <matthew.auld@intel.com>
Wed, 18 Oct 2023 12:34:24 +0000 (13:34 +0100)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Thu, 21 Dec 2023 16:43:19 +0000 (11:43 -0500)
commitbf6d941c06c9681d0f3d8380e7093d7f79d3eef6
tree597fda0dcdfbddfaa0cb1493794a6ae4a3db7343
parent9b49762740e3f2c240877437116635e73718cd47
drm/xe: fix pat[2] programming with 2M/1G pages

Bit 7 in the leaf node is normally programmed with pat[2], however with
2M/1G pages that same bit in the PDE/PDPE also toggles 2M/1G pages. For
2M/1G entries the pat[2] is rather moved to bit 12, which is now free
given that the address must be aligned to 2M or 1G, leaving bit 7 for
toggling 2M/1G pages.

Bspec: 59510, 45038
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drivers/gpu/drm/xe/xe_bo.h
drivers/gpu/drm/xe/xe_vm.c