ARM: dts: aspeed: bletchley: Enable wdtrst1
authorPotin Lai <potin.lai.pt@gmail.com>
Mon, 26 Dec 2022 05:45:35 +0000 (13:45 +0800)
committerJoel Stanley <joel@jms.id.au>
Mon, 23 Jan 2023 03:46:49 +0000 (14:16 +1030)
commitc021d9fe410adadf35a835098073e4528f2db728
tree88ddbe0601ac612c8084018704ed61e5d6320531
parent107fb95f7ba14f38003218c7e340d8431c2e1d50
ARM: dts: aspeed: bletchley: Enable wdtrst1

Enable WDTRST1 external signal to send a reset pulse to peripherals while
BMC reset.

Signed-off-by: Potin Lai <potin.lai.pt@gmail.com>
Reviewed-by: Patrick Williams <patrick@stwcx.xyz>
Link: https://lore.kernel.org/r/20221226054535.2836110-3-potin.lai.pt@gmail.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts