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(parent: c4e792d) | patch
ARM: 9057/1: cache-v7: add missing ISB after cache level selection
authorArd Biesheuvel <ardb@kernel.org>
Thu, 11 Feb 2021 08:19:46 +0000 (09:19 +0100)
committerRussell King <rmk+kernel@armlinux.org.uk>
Tue, 9 Mar 2021 10:25:17 +0000 (10:25 +0000)
commitc0e50736e826b51ddc437e6cf0dc68f07e4ad16b
tree06b10b3e8e4f25d4792eb8e6e1ded3c1297fd6fatree | snapshot
parentc4e792d1acce31c2eb7b9193ab06ab94de05bf42commit | diff
ARM: 9057/1: cache-v7: add missing ISB after cache level selection

A write to CSSELR needs to complete before its results can be observed
via CCSIDR. So add a ISB to ensure that this is the case.

Acked-by: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
arch/arm/mm/cache-v7.S diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git