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(parent: a4a0ce2) | patch
tools/testing/cxl: Mock one level of switches
authorDan Williams <dan.j.williams@intel.com>
Mon, 24 Jan 2022 00:32:01 +0000 (16:32 -0800)
committerDan Williams <dan.j.williams@intel.com>
Wed, 9 Feb 2022 06:57:33 +0000 (22:57 -0800)
commitc1915142e8c1168498c8b08cd4e02728d1c33563
treebec52ff5ee6a7ac5241587ac282d3d1808a9d8bbtree | snapshot
parenta4a0ce242fcd7022349212c4e2f795762e6ff050commit | diff
tools/testing/cxl: Mock one level of switches

The CXL port enumeration process adds intermediate CXL ports that are
discovered between "root" CXL ports enumerated by 'cxl_acpi' and
endpoints enumerated by 'cxl_pci + cxl_mem'. Test the dynamic discovery
of intermediate switch ports in a CXL topology.

Link: https://lore.kernel.org/r/164298432189.3018233.13142151550113000967.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
tools/testing/cxl/test/cxl.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git