drm/amd/display: Send PQ bit in AMD VSIF
authorKrunoslav Kovac <krunoslav.kovac@amd.com>
Wed, 1 Nov 2023 19:59:56 +0000 (15:59 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 17 Nov 2023 14:30:50 +0000 (09:30 -0500)
commitc21a764a98cb59d673cad3da64f35f4dec951951
treee2aa1bddfcde1b3fa72177be5d7874ea6deb0304
parentcc6201b773f12388c234aa10145322ccc429959e
drm/amd/display: Send PQ bit in AMD VSIF

[WHY & HOW]
PB9 bit 5 was added to signal PQ EOTF in AMD vendor specific infoframe.
This change sets it when appropriate.

Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Krunoslav Kovac <krunoslav.kovac@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/modules/freesync/freesync.c