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mailbox: qcom: Add support for SDX55 APCS IPC
authorManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Mon, 18 Jan 2021 04:11:53 +0000 (09:41 +0530)
committerJassi Brar <jaswinder.singh@linaro.org>
Mon, 15 Feb 2021 05:25:35 +0000 (23:25 -0600)
commitc319f78cba83bb0475cbcbf221492c651bd35b2b
tree222e7483dff81f6199543618be94c56e682aee02tree | snapshot
parent0d17014e91898b20fb5010a03470f11fee3c6391commit | diff
mailbox: qcom: Add support for SDX55 APCS IPC

In SDX55, the IPC bits are located in the APCS GCC block. Also, this block
can provide clock functionality. Hence, add support for IPC with correct
offset and name of the clock provider.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
drivers/mailbox/qcom-apcs-ipc-mailbox.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git