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(parent: d19d6ff) | patch
target/i386: Support Arch LBR in CPUID enumeration
authorYang Weijiang <weijiang.yang@intel.com>
Tue, 15 Feb 2022 19:52:58 +0000 (14:52 -0500)
committerPaolo Bonzini <pbonzini@redhat.com>
Sat, 14 May 2022 10:32:41 +0000 (12:32 +0200)
commitc3c67679f65903b7d1fe25da8fc4e163878ab2b9
tree18b04e655a77ca60f39ec21ac1bcfa06e8653895tree | snapshot
parentd19d6ffa07100f5015dc1c708d6c811354a13d7fcommit | diff
target/i386: Support Arch LBR in CPUID enumeration

If CPUID.(EAX=07H, ECX=0):EDX[19] is set to 1, the processor
supports Architectural LBRs. In this case, CPUID leaf 01CH
indicates details of the Architectural LBRs capabilities.
XSAVE support for Architectural LBRs is enumerated in
CPUID.(EAX=0DH, ECX=0FH).

Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
Message-Id: <20220215195258.29149-9-weijiang.yang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
target/i386/cpu.c diff | blob | history
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