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(parent: 6cb5cec) | patch
drm/amd/display: Enable timing sync on DCN32
authorAlvin Lee <Alvin.Lee2@amd.com>
Thu, 20 Oct 2022 15:46:51 +0000 (11:46 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 2 Nov 2022 20:51:02 +0000 (16:51 -0400)
commitc3d3f35b725bf9c93bec6d3c056f6bb7cfd27403
treea11225d0651dad852e11055585a539491737ceactree | snapshot
parent6cb5cec16c380be4cf9776a8c23b72e9fe742fd1commit | diff
drm/amd/display: Enable timing sync on DCN32

Missed enabling timing sync on DCN32 because DCN32 has a different DML
param.

Tested-by: Mark Broadworth <mark.broadworth@amd.com>
Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git