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riscv: dts: sophgo: add initial CV1800B SoC device tree
authorJisheng Zhang <jszhang@kernel.org>
Fri, 6 Oct 2023 12:14:48 +0000 (20:14 +0800)
committerConor Dooley <conor.dooley@microchip.com>
Sat, 7 Oct 2023 13:17:12 +0000 (14:17 +0100)
commitc3dffa879ccad5f0b08deedc2c428f4f7ae7f8e6
treee7a53c21d246b9d921660ec4d989317e01f77658tree | snapshot
parent32ecb28b8e60f75e45790fd9948470a911b0ef7dcommit | diff
riscv: dts: sophgo: add initial CV1800B SoC device tree

Add initial device tree for the CV1800B RISC-V SoC by SOPHGO.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Acked-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
arch/riscv/boot/dts/sophgo/cv1800b.dtsi [new file with mode: 0644] blob
ep93xx device tree rework repo: git://git.maquefel.me/linux.git