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(parent: 3f833f8) | patch
target/riscv: Add support for Control Transfer Records extension CSRs.
authorRajnesh Kanwal <rkanwal@rivosinc.com>
Wed, 5 Feb 2025 11:18:47 +0000 (11:18 +0000)
committerAlistair Francis <alistair.francis@wdc.com>
Tue, 4 Mar 2025 05:42:54 +0000 (15:42 +1000)
commitc48bd18eaeb676a7236030eb9b7984b9244d7750
tree896eb38a23c45d54d05c544d7a728717ed06b522tree | snapshot
parent3f833f8920d815caa6cd0215a5707a03426ba574commit | diff
target/riscv: Add support for Control Transfer Records extension CSRs.

This commit adds support for [m|s|vs]ctrcontrol, sctrstatus and
sctrdepth CSRs handling.

Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250205-b4-ctr_upstream_v6-v6-3-439d8e06c8ef@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.h diff | blob | history
target/riscv/cpu_cfg.h diff | blob | history
target/riscv/csr.c diff | blob | history
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