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(parent: 8f8c793) | patch
target/ppc: 6xx: Set SRRs directly in exception code
authorFabiano Rosas <farosas@linux.ibm.com>
Wed, 9 Feb 2022 08:08:56 +0000 (09:08 +0100)
committerCédric Le Goater <clg@kaod.org>
Wed, 9 Feb 2022 08:08:56 +0000 (09:08 +0100)
commitc50eaed135216597cd75f71cec79ae28a7996c06
treea4d1adf0afceff902efa362d20f0e3f37b8a9097tree | snapshot
parent8f8c7932d4be3fe4dc0fb9540c48132de7382cabcommit | diff
target/ppc: 6xx: Set SRRs directly in exception code

The 6xx CPUs don't have alternate/hypervisor Save and Restore
Registers, so we can set SRR0 and SRR1 directly.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220203200957.1434641-12-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
target/ppc/excp_helper.c diff | blob | history
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