drm/amd/pm: optimize the link width/speed retrieving V2
authorEvan Quan <evan.quan@amd.com>
Sat, 20 Feb 2021 03:58:51 +0000 (11:58 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 2 Mar 2021 19:05:28 +0000 (14:05 -0500)
commitc524c1c9a78f12137da0447e085411cbbd89ab0b
treed6bc79ab6aa8842a24b43262a2b52acbf1debbb3
parent7d6c13ef466d817418a04d5f7cd1e572a63b8c57
drm/amd/pm: optimize the link width/speed retrieving V2

By using the information provided by PMFW when available.

V2: put those structures shared around SMU V11 ASICs in
    smu_v11_0.h

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c