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(parent: ab78cbc) | patch
sh: pci: Set pci_cache_line_size on SH7780 via the PCICLS register.
authorPaul Mundt <lethal@linux-sh.org>
Fri, 17 Apr 2009 07:38:00 +0000 (16:38 +0900)
committerPaul Mundt <lethal@linux-sh.org>
Fri, 17 Apr 2009 07:38:00 +0000 (16:38 +0900)
commitc66c1d79a94a7a302e2dc6c93da40902423eac3e
treee29bf59d813f623b3a71f5ccb2d0f8ac16fec051tree | snapshot
parentab78cbcf6877334fc20868b7df7887349e2e01c8commit | diff
sh: pci: Set pci_cache_line_size on SH7780 via the PCICLS register.

The SH7780 PCIC contains a read-only cache line size register that we can
derive pci_cache_line_size from. So, make sure that the software idea of
the cache line size actually matches the host controller's idea.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
arch/sh/drivers/pci/pci-sh7780.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git