drm/i915/dg2: Add DG2-specific shadow register table
authorMatt Roper <matthew.d.roper@intel.com>
Fri, 10 Sep 2021 20:10:30 +0000 (13:10 -0700)
committerMatt Roper <matthew.d.roper@intel.com>
Wed, 22 Sep 2021 00:16:27 +0000 (17:16 -0700)
commitc74e66d47e883d7fa345a74154d355a297b1abbd
tree516821111d0c9036b68f4eb9a361d2f3f16892ff
parente5b32ae34b02c74d3327789281b88c1e59fdca30
drm/i915/dg2: Add DG2-specific shadow register table

We thought the DG2 table of shadowed registers would be the same as the
gen12/xehp table, but it turns out that there are a few minor
differences that require us to define a new DG2-specific table:
 * One register is removed (0xC4D4)
 * One register is added (0xC4E0)

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210910201030.3436066-7-matthew.d.roper@intel.com
drivers/gpu/drm/i915/intel_uncore.c
drivers/gpu/drm/i915/selftests/intel_uncore.c