arm64: dts: hi3798cv200: add cache info

arm64: dts: hi3798cv200: add cache info

During boot, the kernel complains:

[    0.044029] cacheinfo: Unable to detect cache hierarchy for CPU 0

So add L1/L2 cache info to the dts according to the datasheet. (32KiB L1
i-cache + 32 KiB L1 d-cache + 512 KiB L2 unified cache)

With this patch, the line above is gone and the following info is added
to the output of `lscpu`:

Caches (sum of all):
  L1d:                   128 KiB (4 instances)
  L1i:                   128 KiB (4 instances)
  L2:                    512 KiB (1 instance)

Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
Link: https://lore.kernel.org/r/20240219-cache-v3-3-a33c57534ae9@outlook.com
[krzysztof: drop Fixes/cc-stable, because this is a missing feature, not
 a fix]
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>