target/mips: Fix cycle counter timing calculations
authorSimon Burge <simonb@NetBSD.org>
Mon, 13 Dec 2021 13:51:27 +0000 (00:51 +1100)
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>
Mon, 7 Mar 2022 19:34:17 +0000 (20:34 +0100)
commitc8aeab3a09b51f828eaa50b994434dbfb3f626b8
tree5b1cd7d3464d76870f219f22a9048c27120af5ad
parentb49872aa8fc0f3f5a3036cc37aa2cb5c92866f33
target/mips: Fix cycle counter timing calculations

The cp0_count_ns value is calculated from the CP0_COUNT_RATE_DEFAULT
constant in target/mips/cpu.c.  The cycle counter resolution is defined
per-CPU in target/mips/cpu-defs.c.inc; use this value for calculating
cp0_count_ns.  Fixings timing problems on guest OSs for the 20Kc CPU
which has a CCRes of 1.

Signed-off-by: Simon Burge <simonb@NetBSD.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211213135125.18378-1-simonb@NetBSD.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
target/mips/cpu.c