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(parent: 6cc7a3a) | patch
target-arm: Convert cp15 c3 register
authorPeter Maydell <peter.maydell@linaro.org>
Wed, 20 Jun 2012 11:57:13 +0000 (11:57 +0000)
committerPeter Maydell <peter.maydell@linaro.org>
Wed, 20 Jun 2012 12:05:44 +0000 (12:05 +0000)
commitc983fe6cf199f919e1d9b24c86167e46ac20d8b8
tree3c2e233ed6e373adfc4f29165f4ebd53b1114dadtree | snapshot
parent6cc7a3aee6259ca9d94312b1af0255c92a30fe34commit | diff
target-arm: Convert cp15 c3 register

Convert the cp15 c3 register (MMU domain access control
or MPU write buffer control). NB that this is horribly
underdecoded for modern cores (should be crn=3,crm=0,
opc1=0,opc2=0) but this change preserves the existing
QEMU behaviour.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm/helper.c diff | blob | history
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