clk: ingenic: Mark critical clocks in Ingenic SoCs
authorAidan MacDonald <aidanmacdonald.0x0@gmail.com>
Thu, 28 Apr 2022 16:44:53 +0000 (17:44 +0100)
committerStephen Boyd <sboyd@kernel.org>
Wed, 18 May 2022 20:56:22 +0000 (13:56 -0700)
commitca54d06fcacfdeb0b07acb4c6469a96fb02a9b44
tree096e8d883fa8a0e6d9defd626fa28ff720d78181
parentbacf743e925d10076c0ba9b9289d0e827c3db7f1
clk: ingenic: Mark critical clocks in Ingenic SoCs

Consider CPU, L2 cache, and memory clocks as critical to prevent
them -- and the parent clocks -- from being automatically gated,
since nothing calls clk_get() on these clocks.

Gating the CPU clock hangs the processor, and gating memory makes
external DRAM inaccessible. Normal kernel code can't hope to deal
with either situation so those clocks have to be critical.

The L2 cache is required only if caches are running, and could be
gated if the kernel takes care to flush and disable caches before
gating the clock. There's no mechanism to do this, and probably no
reason to do it, so it's simpler to mark the L2 cache as critical.

Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20220428164454.17908-3-aidanmacdonald.0x0@gmail.com
Tested-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> # On X1000 and X1830
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/ingenic/jz4725b-cgu.c
drivers/clk/ingenic/jz4740-cgu.c
drivers/clk/ingenic/jz4760-cgu.c
drivers/clk/ingenic/jz4770-cgu.c
drivers/clk/ingenic/jz4780-cgu.c
drivers/clk/ingenic/x1000-cgu.c
drivers/clk/ingenic/x1830-cgu.c