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(parent: 00f05c0) | patch
hw/ssi: Add a model of Xilinx Versal's OSPI flash memory controller
authorFrancisco Iglesias <francisco.iglesias@xilinx.com>
Fri, 21 Jan 2022 16:11:37 +0000 (16:11 +0000)
committerPeter Maydell <peter.maydell@linaro.org>
Fri, 28 Jan 2022 14:29:46 +0000 (14:29 +0000)
commitcbb45ff038cdbfcc8af158191405e2597f28c562
treea0c2702a94b931d363b89f1bfebed6a13cd0aa2etree | snapshot
parent00f05c02f9e7342fb423110061bdf66921fe80b2commit | diff
hw/ssi: Add a model of Xilinx Versal's OSPI flash memory controller

Add a model of Xilinx Versal's OSPI flash memory controller.

Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20220121161141.14389-7-francisco.iglesias@xilinx.com
[PMM: fixed indent]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
hw/ssi/meson.build diff | blob | history
hw/ssi/xlnx-versal-ospi.c [new file with mode: 0644] blob
include/hw/ssi/xlnx-versal-ospi.h [new file with mode: 0644] blob
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