target/riscv: add support for Zcmt extension
authorWeiwei Li <liweiwei@iscas.ac.cn>
Tue, 7 Mar 2023 08:14:00 +0000 (16:14 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 5 May 2023 00:49:50 +0000 (10:49 +1000)
commitce3af0bbbcdfa754cd50f278e83a750730a67c25
treecca4a80788737530a5991021c1118c5077c0cfef
parent193eb522e4083d8e84c3fae443fd98bc300b95d0
target/riscv: add support for Zcmt extension

Add encode, trans* functions and helper functions support for Zcmt
instrutions.
Add support for jvt csr.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-8-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.h
target/riscv/cpu_bits.h
target/riscv/csr.c
target/riscv/helper.h
target/riscv/insn16.decode
target/riscv/insn_trans/trans_rvzce.c.inc
target/riscv/machine.c
target/riscv/meson.build
target/riscv/zce_helper.c [new file with mode: 0644]