tty: serial: fsl_lpuart: optimize the timer based EOP logic

tty: serial: fsl_lpuart: optimize the timer based EOP logic

DMA transfer may end prematurely due to the DMA Rx timeout even during an
active transfer because a constant timeout does not accurately simulate an
EOP (End Of Package) event. This patch uses a timer to simulate the
hardware EOP event. The timer should only complete a DMA transfer once the
idle period satisfies a specified interval which is baud rate dependent.
The problem has been observed with low baud rates but could occur also
with high baud rates.

Make the DMA Rx timeout baud rate dependent and check the DMA residue count
before copying data to the TTY buffer. If the residue count remains
unchanged since the last interrupt, that indicates no new data was
received. In this case, the DMA should complete as an EOP event. Otherwise,
new data was received during the interval and the EOP condition is not met
so restart the DMA Rx timeout

Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Link: https://lore.kernel.org/r/20230510203359.1353469-1-shenwei.wang@nxp.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>