target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
authorAnup Patel <anup.patel@wdc.com>
Fri, 4 Feb 2022 17:46:46 +0000 (23:16 +0530)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 16 Feb 2022 02:24:19 +0000 (12:24 +1000)
commitd028ac7512f1a781a5cba7659a1d25dc972afdd4
treed48604427fc22e80246f43efbc8852e2fe2a7c39
parent43dc93af36dced9d23911be2ed6b0fe82bf3c42c
target/riscv: Implement AIA CSRs for 64 local interrupts on RV32

The AIA specification adds new CSRs for RV32 so that RISC-V hart can
support 64 local interrupts on both RV32 and RV64.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-11-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.h
target/riscv/cpu_helper.c
target/riscv/csr.c
target/riscv/machine.c