hw/cxl/cxl-mailbox-utils: Fix for device DDR5 ECS control feature tables
authorShiju Jose <shiju.jose@huawei.com>
Mon, 14 Oct 2024 12:19:00 +0000 (13:19 +0100)
committerMichael S. Tsirkin <mst@redhat.com>
Mon, 4 Nov 2024 21:03:24 +0000 (16:03 -0500)
commitd1853190db5c59ad5b0537a2ac59c8d4494cbd98
tree4439ee88b3b624759b77249f43549382fd15ba2c
parent80ee960f8d646505385bce8ed143a9bb8ea36d1d
hw/cxl/cxl-mailbox-utils: Fix for device DDR5 ECS control feature tables

CXL spec 3.1 section 8.2.9.9.11.2 describes the DDR5 Error Check Scrub (ECS)
control feature.

ECS log capabilities field in following ECS tables, which is common for all
memory media FRUs in a CXL device.

Fix struct CXLMemECSReadAttrs and struct CXLMemECSWriteAttrs to make
log entry type field common.

Fixes: 2d41ce38fb9a ("hw/cxl/cxl-mailbox-utils: Add device DDR5 ECS control feature")
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20241014121902.2146424-6-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
hw/cxl/cxl-mailbox-utils.c
hw/mem/cxl_type3.c
include/hw/cxl/cxl_device.h