clk: imx8mm: remove SYS PLL 1/2 clock gates
authorPeng Fan <peng.fan@nxp.com>
Fri, 25 Feb 2022 08:17:31 +0000 (16:17 +0800)
committerAbel Vesa <abel.vesa@nxp.com>
Fri, 4 Mar 2022 15:06:29 +0000 (17:06 +0200)
commitd25cbd3e392730f459f1fbf5f959c16b460a59ca
treee5d8ad309098a5dc2227fd1f7459be837e1ace2d
parent24defbe194b650218680fcd9dec8cd103537b531
clk: imx8mm: remove SYS PLL 1/2 clock gates

Remove the PLL 1/2 gates as it make AMP clock management harder without
obvious benifit.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20220225081733.2294166-2-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
drivers/clk/imx/clk-imx8mm.c