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riscv/opentitan: Update the OpenTitan memory layout
authorAlistair Francis <alistair.francis@wdc.com>
Tue, 15 Dec 2020 01:56:54 +0000 (17:56 -0800)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 18 Dec 2020 05:56:44 +0000 (21:56 -0800)
commitd31e970a01e7399b9cd43ec0dc00c857d968987e
treef7e62273c6e9697bd2cc28a88e4aad8ef21adc69tree | snapshot
parent3ed2b8ac2dacc22c088ec5793ecde31db2fa0414commit | diff
riscv/opentitan: Update the OpenTitan memory layout

OpenTitan is currently only avalible on an FPGA platform and the memory
addresses have changed. Update to use the new memory addresses.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 8eb65314830a75d0fea3fccf77bc45b8ddd01c42.1607982831.git.alistair.francis@wdc.com
hw/riscv/opentitan.c diff | blob | history
include/hw/riscv/opentitan.h diff | blob | history
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