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(parent: cea3e94) | patch
phy: qcom-qmp: qserdes-lane-shared: Add v6 register offsets
authorAbel Vesa <abel.vesa@linaro.org>
Wed, 8 Feb 2023 18:00:16 +0000 (20:00 +0200)
committerVinod Koul <vkoul@kernel.org>
Fri, 10 Feb 2023 16:58:00 +0000 (22:28 +0530)
commitd38360e12fbc1b41ae6a2a243ce0b01ce27e5cab
tree79d6b10a49cee87c4e8a945e237f801304fcbd11tree | snapshot
parentcea3e9435e63237aa010e5868f9a38cfccec89f1commit | diff
phy: qcom-qmp: qserdes-lane-shared: Add v6 register offsets

The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for
PCIE g4x2. Add the new lane shared PCIE specific offsets in a dedicated
header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230208180020.2761766-8-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h [new file with mode: 0644] blob
drivers/phy/qualcomm/phy-qcom-qmp.h diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git