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(parent: 3a6f8f6) | patch
target/riscv: vector bitwise logical instructions
authorLIU Zhiwei <zhiwei_liu@c-sky.com>
Wed, 1 Jul 2020 15:25:01 +0000 (23:25 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Thu, 2 Jul 2020 16:19:33 +0000 (09:19 -0700)
commitd3842924cf93d104f691c5ea9090d6700ccef281
treef49bb4430b15efdbb2668e1c01799c11d47cac2ftree | snapshot
parent3a6f8f68ad2f4a22d9ae8287f336b5dcc80b6448commit | diff
target/riscv: vector bitwise logical instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-14-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/helper.h diff | blob | history
target/riscv/insn32.decode diff | blob | history
target/riscv/insn_trans/trans_rvv.inc.c diff | blob | history
target/riscv/vector_helper.c diff | blob | history
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