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riscv: dts: starfive: Add JH7100 cache controller
authorEmil Renner Berthing <emil.renner.berthing@canonical.com>
Thu, 30 Nov 2023 15:19:28 +0000 (16:19 +0100)
committerConor Dooley <conor.dooley@microchip.com>
Wed, 13 Dec 2023 15:50:23 +0000 (15:50 +0000)
commitd4b95c445cab0fb583eed7caafbc1b734f6a3a59
treebe378d740f95deca4270369291edb73d6fe1fc2ctree | snapshot
parentba0074972ee9b3231b3de44650583654422e9758commit | diff
riscv: dts: starfive: Add JH7100 cache controller

The StarFive JH7100 SoC also features the SiFive L2 cache controller,
so add the device tree nodes for it.

Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
arch/riscv/boot/dts/starfive/jh7100.dtsi diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git