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(parent: db77d85) | patch
target-mips: correct MTC0 instruction on MIPS64
authorLeon Alrae <leon.alrae@imgtec.com>
Wed, 9 Sep 2015 11:44:25 +0000 (12:44 +0100)
committerLeon Alrae <leon.alrae@imgtec.com>
Fri, 18 Sep 2015 08:20:48 +0000 (09:20 +0100)
commitd54a299b83a07642c85a22bfe19b69ca4def9ec4
treee81c778717e27d4ee9525482136669666f7daa70tree | snapshot
parentdb77d8523909b32d798cd2c80de422b68f9e5c42commit | diff
target-mips: correct MTC0 instruction on MIPS64

MTC0 on a 64-bit processor should move entire 64-bit GPR content to CP0
register.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips/translate.c diff | blob | history
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