drm/xe/gsc: Implement WA 14018094691
authorDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Tue, 26 Mar 2024 22:44:56 +0000 (15:44 -0700)
committerDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Thu, 28 Mar 2024 20:26:31 +0000 (13:26 -0700)
commitd62753a57de2547c72819cc82b76731f04563433
treee78b2994a3eb1c22604e709148cd8c8855e2bdf4
parentaed2c1d70aa008b83c806d33d55b1f782f4fff41
drm/xe/gsc: Implement WA 14018094691

The WA states that we need to keep the primary GT powered up during GSC
load to allow the GSC FW to access its registers. We also need to make
sure that one of the registers is locked before starting the load.

v2: fix location of register def (Matt)

Bspec: 55928
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240326224456.518548-1-daniele.ceraolospurio@intel.com
drivers/gpu/drm/xe/regs/xe_gt_regs.h
drivers/gpu/drm/xe/xe_gsc.c
drivers/gpu/drm/xe/xe_wa_oob.rules