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arm64: dts: hip05: Add L2 cache topology
authorKefeng Wang <wangkefeng.wang@huawei.com>
Fri, 29 Jan 2016 08:39:01 +0000 (16:39 +0800)
committerWei Xu <xuwei5@hisilicon.com>
Thu, 25 Feb 2016 13:15:58 +0000 (21:15 +0800)
commitdbb58d0f79207d35f298b619a87fb81dbcae788d
tree62aca64fcc2c0af61181f1a4f633b8ea4b5fa2e2tree | snapshot
parent92e963f50fc74041b5e9e744c330dca48e04f08dcommit | diff
arm64: dts: hip05: Add L2 cache topology

The Hip05 SoC has four L2 cache for all 16 CPUs, every four cpus
share one L2 cache, add them to the dtsi file so that the cache
hierarchy can be probed.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
arch/arm64/boot/dts/hisilicon/hip05.dtsi diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git