target/riscv: Update pmp_get_tlb_size()
authorWeiwei Li <liweiwei@iscas.ac.cn>
Wed, 17 May 2023 09:15:08 +0000 (17:15 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Tue, 13 Jun 2023 07:06:39 +0000 (17:06 +1000)
commitdc7b599332c26065cd9ff1f2f2cf3ed580ca3dfd
tree7d020eeda81742b034b0ba2be7c7b3f26a7440d8
parentfaf3b5d86ff3b0349ded42f8ef3240d1960b6a1a
target/riscv: Update pmp_get_tlb_size()

PMP entries before (including) the matched PMP entry may only cover partial
of the TLB page, and this may split the page into regions with different
permissions. Such as for PMP0 (0x80000008~0x8000000F, R) and PMP1 (0x80000000~
0x80000FFF, RWX), write access to 0x80000000 will match PMP1. However we cannot
cache the translation result in the TLB since this will make the write access
to 0x80000008 bypass the check of PMP0. So we should check all of them instead
of the matched PMP entry in pmp_get_tlb_size() and set the tlb_size to 1 in
this case.
Set tlb_size to TARGET_PAGE_SIZE if PMP is not support or there is no PMP rules.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517091519.34439-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu_helper.c
target/riscv/pmp.c
target/riscv/pmp.h