EDAC/i10nm: Make more configurations CPU model specific
authorQiuxu Zhuo <qiuxu.zhuo@intel.com>
Fri, 13 Jan 2023 03:28:01 +0000 (11:28 +0800)
committerTony Luck <tony.luck@intel.com>
Wed, 25 Jan 2023 16:17:20 +0000 (08:17 -0800)
commitdd7814b78539416c6e561eeaa0951b3e88ac799e
tree9aefcf6f4c0b58fa1b99fe0d38f1eb55d00ac297
parente4b2bc6616e21f4a7ce4e7452f716e3db8fe66b6
EDAC/i10nm: Make more configurations CPU model specific

The numbers of memory controllers per socket, channels per memory
controller, DIMMs per channel and the triples of bus/device/function
of PCI devices used in i10nm_edac can be CPU model specific.
Add new fields to the structure res_config for above numbers and
triples to make them CPU model specific.

Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Link: https://lore.kernel.org/all/20230113032802.41752-1-qiuxu.zhuo@intel.com
drivers/edac/i10nm_base.c
drivers/edac/skx_common.h