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clk: renesas: r9a07g043: Add GbEthernet clock/reset
authorBiju Das <biju.das.jz@bp.renesas.com>
Sat, 2 Apr 2022 07:46:25 +0000 (08:46 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Wed, 13 Apr 2022 10:30:19 +0000 (12:30 +0200)
commite11f804afc12e1c622f0a6f966fafd05b7022f8a
tree6f92a6c5cb53e2aa408007a90bd919f856f886d1tree | snapshot
parentf201eb84450f98decb1834e73409bb2271441dd7commit | diff
clk: renesas: r9a07g043: Add GbEthernet clock/reset

Add ETH{0,1} clock/reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402074626.25624-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a07g043-cpg.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git