riscv: dts: starfive: visionfive-v1: Setup ethernet phy
authorCristian Ciocaltea <cristian.ciocaltea@collabora.com>
Wed, 20 Dec 2023 21:17:41 +0000 (23:17 +0200)
committerConor Dooley <conor.dooley@microchip.com>
Wed, 31 Jan 2024 12:23:26 +0000 (12:23 +0000)
commite16d3dc0a2d7cd7bd673ce08b39a4239aafe0938
treed5175be6a495bd8e680eeb36995cc1037e56a6bc
parent6e204aa2116cf9677b8b93ba15d7831d98e4a236
riscv: dts: starfive: visionfive-v1: Setup ethernet phy

The StarFive VisionFive V1 SBC uses a Motorcomm YT8521 PHY supporting
RGMII-ID, but requires manual adjustment of the RX internal delay to
work properly.

The default RX delay provided by the driver is 1.95 ns, which proves to
be too high. Applying a 50% reduction seems to mitigate the issue.

Also note this adjustment is not necessary on BeagleV Starlight SBC,
which uses a Microchip PHY.  Hence, there is no indication of a
misbehaviour on the GMAC side, but most likely the issue stems from
the Motorcomm PHY.

While at it, drop the redundant gpio include, which is already provided
by jh7100-common.dtsi.

Co-developed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts