iio: accel: adxl367: Fix alignment for DMA safety
authorJonathan Cameron <Jonathan.Cameron@huawei.com>
Sun, 8 May 2022 17:55:44 +0000 (18:55 +0100)
committerJonathan Cameron <Jonathan.Cameron@huawei.com>
Tue, 14 Jun 2022 10:53:11 +0000 (11:53 +0100)
commite1f956a804df9074fb5de557563d153ae25252e7
treeafcc5ab10fe7f4f45d11c7268e34e8d6f9b84c14
parent46403dcf3a7cbd24b86f809fd79962f4d6b137c5
iio: accel: adxl367: Fix alignment for DMA safety

____cacheline_aligned is insufficient guarantee for non-coherent DMA.
Switch to the updated IIO_DMA_MINALIGN definition.

Update comment to reflect that DMA safety may require separate
cachelines.

Fixes: cbab791c5e2a5 ("iio: accel: add ADXL367 driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Cosmin Tanislav <demonsingur@gmail.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-5-jic23@kernel.org
drivers/iio/accel/adxl367.c
drivers/iio/accel/adxl367_spi.c