cxl/pci: Add debug for DVSEC range init failures
authorDan Williams <dan.j.williams@intel.com>
Tue, 15 Mar 2022 01:22:28 +0000 (18:22 -0700)
committerDan Williams <dan.j.williams@intel.com>
Wed, 13 Apr 2022 02:11:58 +0000 (19:11 -0700)
commite39f9be08d9dfe685c8a325ac1755c04f383effc
tree19b77b6432f6bb9d2d83af20d1fa4e66bc997645
parente08063fb87944b1db963e94b833608318179708d
cxl/pci: Add debug for DVSEC range init failures

In preparation for not treating DVSEC range initialization failures as
fatal to cxl_pci_probe() add individual dev_dbg() statements for each of
the major failure reasons in cxl_dvsec_ranges().

The rationale for cxl_dvsec_ranges() failure not being fatal is that
there is still value for cxl_pci to enable mailbox operations even if
CXL.mem operation is disabled.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ben Widawsky <ben.widawsky@intel.com>
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Link: https://lore.kernel.org/r/164730734812.3806189.2726330688692684104.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
drivers/cxl/pci.c