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(parent: e643cd3) | patch
drm/amd/display: Avoid setting pixel rate divider to N/A
authorTaimur Hassan <Syed.Hassan@amd.com>
Fri, 11 Nov 2022 19:11:00 +0000 (14:11 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 23 Nov 2022 14:47:14 +0000 (09:47 -0500)
commite3aa827e2ab3ec40ca97a3f846892aac81ce5e3c
treea3b686918c8dad7d6f226b1bd20cfe80973cf9b0tree | snapshot
parente643cd384270fd3a4b66f65f15dafc8db0607adccommit | diff
drm/amd/display: Avoid setting pixel rate divider to N/A

[Why]
Pixel rate divider values should never be set to N/A (0xF) as the K1/K2
field is only 1/2 bits wide.

[How]
Set valid divider values for virtual and FRL/DP2 cases.

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c diff | blob | history
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c diff | blob | history
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c diff | blob | history
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git